1. Field of the Invention
The present invention relates to a decoder circuit. This decoder circuit is connected to one of a group of word lines which are arranged in a matrix form. Each word line is connected to a large number of binary cells. By using the decoder circuit according to the present invention, one of a large number of binary cells is selected randomly so as to write or read the data.
2. Description of the Prior Art
A dynamic ramdom access memory MOSFET integrated circuit which is conventionally used so as to write or read the data into or from a great number of storage cells is disclosed in U.S. Pat. No. 3,969,706. In FIG. 10 of U.S. Pat. No. 3,969,706, a decoder circuit is connected to one of a group of word lines which are arranged in a matrix form. Each word line is connected to a plurality of storage cells. The decoder circuit determines whether the decoder circuit selects the word line or not. This decoder circuit includes: a charge up transistor for maintaining the content of input address signals; a power supply switching transistor for controlling a charge up current which is supplied to the charge up transistor; a predetermined number of selection transistors which are connected at a connection node between the charge up transistor and the power supply switching transistor for selecting an output word line, and; a bootstrap transistor which is connected at an opposite side of the connection node with respect to the charge up transistor.
In the above described conventional decoder circuit, when noise is generated in the input address signal at a time when the decoder circuit selects the word line, the selection transistor is activated, and the charges at the connection node between the charge up transistor and the power supply source switching transistor are discharged, so that the selection level of the decoder circuit is decreased and, sometimes, a malfunction is caused.